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    • 专利摘要:
    The invention relates to a time of flight detection sensor comprising a plurality of pixels, each pixel comprising a photosensitive area (PD) and at least two sets (Qi) each comprising: a charge storage area (memi); a transfer transistor (Tmem-j) adapted to control charge transfers from the photosensitive area (PD) to the charge storage area; and reading means (Vri, 23, 25, LECT) capable of non-destructively measuring the quantity of charges stored in the storage area.
    公开号:FR3065320A1
    申请号:FR1753344
    申请日:2017-04-18
    公开日:2018-10-19
    发明作者:Francois Roy
    申请人:STMicroelectronics Crolles 2 SAS；
    IPC主号:
    专利说明:

    (54) FLIGHT TIME DETECTION PIXEL
    The invention relates to a time-of-flight detection sensor comprising a plurality of pixels, each pixel comprising a photosensitive area (PD) and at least two assemblies (Qi) each comprising: a charge storage area (memi); a transfer transistor (Tmem-j) adapted to control charge transfers from the photosensitive area (PD) to the charge storage area; and a reading means (Vri, 23, 25, LECT) capable of non-destructively measuring the quantity of charges stored in the storage area.
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    VrespD Vdd f-p
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    JH Vr3 lr- ' 3 ïsef.j;
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    READ
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    B15739 FR - 16-GR3-0522
    FLIGHT TIME DETECTION PIXEL
    Field
    The present application relates to a distance sensor operating on the principle of time of flight measurement, or TOF (Time Of Flight) sensor.
    Presentation of the prior art
    In a TOF sensor, a light source emits light towards a scene. A time-of-flight detection pixel, or TOF pixel, receives the light returned by a point on the scene conjugated with this pixel. The measurement of the flight time, that is to say the time taken by the light to travel from the light source to the point of the augual scene, is conjugated the pixel, and from this point to the pixel, makes it possible to calculate the distance between the pixel and this point.
    In the case where one seeks to obtain a relief image of a scene, the TOF sensor comprises a matrix of TOF pixels to measure the distance separating each pixel from the point of the scene at which this pixel is conjugated. This makes it possible to obtain a mapping of the distances separating the sensor from the different points of the scene at which the pixels are conjugated, and a
    0 relief images of the scene can then be reconstructed. A problem which arises in such a sensor results from the fact that a pixel conjugated to a point on the scene close to the sensor receives
    B15739 FR - 16-GR3-0522 more light than a pixel conjugated to a point on the scene far from the sensor. This means that for a given illumination time of the sensor (integration time), the amount of light received by the sensor and therefore the amount of charge produced may be insufficient to determine the distance between the sensor and a point distant from the sensor. . The points distant from the sensor are then poorly distinguished in the reconstructed image.
    To avoid this drawback, it is necessary to provide long integration times, which constitutes a problem, in particular in the case of analysis of mobile objects.
    summary
    We seek here to avoid the forecast of systematically long integration times.
    Thus, one embodiment plans to carry out analyzes during moderate integration times, to transfer the photogenerated charges into storage areas, to read the quantities of charges stored in a non-destructive manner, and to repeat the phases of integration, transfer and reading if the first reading (s) reveal insufficient quantities of stored charges. Thus, the integration time is dynamically adapted to the quantity of photogenerated charges.
    More particularly, one embodiment provides a time-of-flight detection sensor comprising a plurality of pixels, each pixel comprising a photosensitive area and at least two sets each comprising: a charge storage area; a transfer transistor adapted to control charge transfers from the photosensitive zone to the charge storage zone; and a reading means capable of non-destructively measuring the quantity of charges stored in the storage area.
    According to one embodiment, the reading means comprises: a reading transistor whose body corresponds to the charge storage area; a constant current source supplying the read transistor; and means for measuring the voltage across the transistor.
    B15739 FR - 16-GR3-0522
    According to one embodiment, the sensor further comprises control means for repeating a transfer of charges to the storage area if the quantity of charges transferred is insufficient to be measured.
    According to one embodiment, each read transistor is coupled to the current source via a selection transistor.
    According to one embodiment, each storage area contains an insulated conductive reset wall.
    According to one embodiment, the sensor comprises a source for transmitting a periodic light signal, and means adapted to synchronize said source and control potentials applied to the transistor gates of each pixel.
    According to one embodiment, a pixel of the sensor comprises a semiconductor substrate and, in the pixel, the photosensitive zone comprises a first layer doped with a first type of conductivity; each charge storage zone extends from an edge of the photosensitive zone, from a first portion of the first layer coated with the gate of the corresponding transfer transistor, the charge storage zone comprising a more highly doped well of the first type as the first layer, and being delimited laterally by two insulated vertical conductive walls, parallel and facing each other; for each box, an annular grid covers a portion of said box and surrounds a heavily doped area of the second type penetrating into the box and being coupled to a constant current source of the sensor; and a second doped layer of the second type covers the charge storage areas and the photosensitive area with the exception of the portions coated with grids.
    According to one embodiment, each storage zone further comprises an insulated vertical conductive wall for resetting, disposed between said two insulated conductive vertical walls, in a portion of the box other than the coated portion of the annular grid (63).
    B15739 FR - 16-GR3-0522
    According to one embodiment, each first portion of the first layer comprises a first intermediate zone adjacent to the corresponding storage zone, the first intermediate zone being doped with the first type, more strongly than the rest of the first layer and less strongly than the storage area cabinet.
    According to one embodiment, each charge storage zone comprises a second intermediate zone, interposed between the box of the storage zone and the photosensitive zone, the second intermediate zone being doped with the first type, more strongly than the first portion and less strongly than the box.
    According to one embodiment, the photosensitive zone has the shape of a square in top view, and each storage zone extends along an edge of the photosensitive zone.
    According to one embodiment, the first layer rests on a portion of the doped substrate of the second type and whose doping level decreases as it approaches the first layer.
    According to one embodiment, a pixel of the sensor further comprises a reset zone more strongly doped with the first type than the photosensitive zone, extending from an edge of the photosensitive zone, from a second portion of the first layer coated with a second grid.
    According to one embodiment, the photosensitive zone further comprises a charge collection zone comprising a central portion disposed substantially in the center of the photosensitive zone, and arms extending from this central portion, between the grids coating said said portions of the first layer.
    According to one embodiment, the pixel is intended to receive a periodic light signal, and the grids coating said portions of the first layer are made of materials transparent to the wavelengths of the received periodic signal.
    B15739 FR - 16-GR3-0522
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures among which:
    Figure 1 is a top view schematically showing an example of a TOF sensor;
    FIG. 2 represents an embodiment of a TOF pixel circuit;
    Figure 3 is a timing diagram illustrating an operating mode of the pixel of Figure 2;
    FIGS. 4A to 4D schematically represent an embodiment of the TOF pixel of FIG. 2; and FIGS. 5A to 5C schematically illustrate the evolution of the electrostatic potentials in various regions of the pixel of FIGS. 4A to 4D during a charge transfer step.
    detailed description
    The same elements have been designated by the same references in the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed.
    In the following description, the terms above, under, upper, lower, vertical, etc., reference is made to the orientation of the elements concerned in the corresponding figures. Unless otherwise specified, the expressions substantially and approximately mean to the nearest 10%, preferably to the nearest 5%.
    Figure 1 is a schematic top view of an example of a TOF sensor. The sensor 1 comprises a matrix 3 of TOF pixels, for example a matrix of 1000 rows by 1000 columns. The matrix 3 is associated with a line decoder 7 and with a column decoder 9. The line decoder 7 provides signals 11 making it possible to select one or the other of the lines
    B15739 FR - 16-GR3-0522 of the matrix. The column decoder 9 makes it possible to read the information of the pixels of a selected row. The line decoder 7 and the column decoder 9 are controlled by signals 13 supplied by a control and processing circuit 15. The control and processing circuit 15 comprises, for example, a processor associated with one or more memories. The sensor 1 is associated with a light source 17, for example a laser, to illuminate a scene from which it is desired to obtain the image in relief. The light source 17 is connected to the control and processing means 15 to synchronize the control signals applied to the TOF pixels of the matrix 3 and the light source 17.
    In the following description, we are interested in the case of a sensor 1 in which the light source 17 emits a sinusoidal signal Lg whose frequency can be between 20 and 160 MHz, for example 25 MHz. For each pixel, the phase shift détermine is determined between the light signal Lg emitted and the light signal Lg received. The distance separating the pixel from its conjugate point is then determined from this phase shift φ.
    FIG. 2 represents an embodiment in the form of a circuit of a TOF pixel.
    The TOF pixel comprises a photosensitive element such as a photodiode PD, one terminal of which is connected to a node 21 and the other terminal of which is connected to a supply rail set to a low reference potential, for example ground. The node 21 is coupled to a reading node LECT by means of three identical sets of transfer, storage and reading Qg, Qg and Q3 in parallel. Each set Qg, with i equal 1, 2 or 3 in this example, comprises an N channel transfer MOS transistor, Tmemg, a charge storage area memg, a P channel read MOS transistor, Trg, and a transistor Selection P-channel MOS, Tselg. The Trg and Tselg transistors are connected in series. The drain of the transistor Trg is connected to a supply rail set to low potential, and the source of the transistor Trg is connected to the drain of the transistor Tselg, the transistor Trg being controlled by a signal Vrg. The source of
    B15739 FR - 16-GR3-0522 Tselp transistor is connected to the LECT read node, the Tselp transistor being controlled by a Vselp signal. The source of the transistor Tmemp is connected to the node 21 of the photosensitive element, and the drain of the transistor Tmemp is coupled to the storage area memp, the transistor Tmemp being controlled by a signal Vmemp applied to its gate. The body region of the transistor Trp corresponds to at least part of the memp storage area. The memp storage zone also comprises a terminal for applying a reset signal Vres.
    The threshold voltage of the read transistor Trp depends on the quantity of charges injected into the charge storage area. The determination of this threshold voltage therefore constitutes a non-destructive means of measuring this quantity of charges.
    The TOF pixel further comprises an N-channel MOS transistor, Trespp, for resetting the photosensitive element PD to zero. The source of the Trespp transistor is connected to node 21 and the drain of the Trespp transistor is connected to a supply rail set to a high reference potential, for example the supply potential Vdd. The Trespp transistor is controlled by a Vrespp signal applied to its gate.
    To determine the phase shift φ between a light signal emitted Lp and a light signal received Lp, the signal Lp is sampled by transferring, successively and at regular intervals during an integration phase, photogenerated charges in the photosensitive element PD towards the zones memp storage then memg and finally menu ·, these transfers being controlled by the corresponding Tmemp transistors. The total duration for carrying out all of these three successive transfers is equal to one period of the signals Lp and Lp, and all of these three successive transfers are repeated a determined number of times, for example 1000 to 100,000 times. Each charge transfer from the photosensitive zone PD to a memp zone causes a modification of the potential in this memp zone. Because the body of the read transistor Trp is included in the corresponding memp storage area, this change in potential
    B15739 FR - 16-GR3-0522 causes a modification of the threshold voltage of the transistor. Thus, a phase of reading the charges accumulated in the storage zones consists in measuring the threshold voltages of the transistors Tr-j_. Advantageously, this reading of the charges accumulated in the memory areas is not destructive. It is therefore possible to repeat the integration, transfer and read operations until a measurable load is transferred to the charge storage area.
    The read node is coupled to a read and control circuit (READ & CONTROL) 25, which in particular controls the reset signals Vres of the storage areas as a function of the signals read.
    FIG. 3 represents chronograms of the light signal Lg emitted by the light source 17 associated with the sensor 1, of the light signal Lg received by the pixel TOF, and of the digital signals Vrespp, Vmem-j_, Vselg, Vr-j_ and Vres during 'an integration phase and during a reading phase, at successive times tp to t] _g.
    In operation, by default, the signals Vrespp, Vmem-j_, and Vres are at a low level and the signals Vselg are at a high level so that the transistors Trespp, Tmemg, Very and Tselg are in the blocked state. Because the transistors Tselg are in the off state, the source of each transistor Trg is disconnected from the read node LECT, and, by default, the signals Vr-j_ can be at a low level such as the transistors Tr-j_ correspondents are in the on state.
    First of all, the photosensitive element PD is reset to zero by putting the transistor Trespp in the on state between instants tg and t] _. At time t] _, the transistor Trespp is returned to the off state and a phase of integration of the pixel, synchronized on the signal Lg, can begin. For example, the Vrespp signal is at a potential of 2 V in the on state, and at a potential of - 1 V in the blocked state.
    During the integration phase, the photogenerated electrons in the photosensitive element PD are transferred to
    B15739 FR - 16-GR3-0522 memg storage areas. For this, the transfer transistors Tmemg are set to the state each passing in turn between respective instants tg and ίβ, tg and ίβ, and tg and. All of these three transfers are then repeated a determined number of times.
    From the instant tg corresponding to the end of the integration phase and the start of a reading phase, the non-destructive reading of the electrons accumulated in each of the storage areas memg is carried out.
    A reading of the memg storage areas is carried out as follows, for each set Qg successively. The selection transistor Tselg is set to the on state to couple the source of the transistor Trg corresponding to the read node LECT. While the transistor Tselg is in the conducting state, the signal Vrg initially in the low state, for example at ground potential, is set to the high state. As shown in Figure 2, a current source 23 connected between the PLAY node and the supply rail Vdd, then provides a current ipect 'F or example 1 μΑ which flows between the source and the drain of transistor Trg. Because a determined current flows in the transistor and that its gate and drain voltages are fixed, the source voltage can only take a single value which depends on the threshold voltage of the transistor, therefore on the amount of charges accumulated in the corresponding memg area. A first potential Vg whose value depends on the threshold voltage of the transistor Trg is then measured at the LECT node. This first potential Vg is stored, for example by the reading and control means 25. The signal Vrg applied to the gate of the transistor Trg is returned to the low state and the transistor Tselg is returned to the blocked state. More particularly, in the example of FIG. 3, the transistor Tselg is set to the on state from the instant tg to the instant tg, the transistor Tselg is set to the on state from the instant tgg to l 'instant tgg, and the transistor Tselg is put in the passing state from instant tgg to instant tgg.
    B15739 FR - 16-GR3-0522
    A reset phase of the storage areas mem-j_ is then carried out if the quantities of charges stored are sufficient. In this embodiment, the reset phase of the mem-j_ zones is carried out, between the instants t] _3 and t] _4, by switching the signal Vres several times between its low state and its high state. A second reading of the storage areas can then be carried out in order to implement a correlated double sampling (CDS of the English Correlated Double Sampling) of each storage area so as to eliminate part of the noise as is well known in the art. skilled in the art. In the example shown, the second reading of storage area memp memg, menu · is carried out between the instants respectively tig and t] _5, t] _6 and t] _ç, and t] _g and t] _g.
    After the first reading of the mem-j_ areas of a pixel, the sum of the first potentials V-j_ is calculated, for example by the reading and control means 25. This sum makes it possible to roughly evaluate the quantity of light received by the pixel during the previous integration phase. It is then possible to know, before resetting the storage areas mem-j_, if this quantity of light is sufficient so that the point of the scene conjugated with this pixel can be distinguished in the reconstructed image. For this, the sum of the first potentials V-j_ is for example compared with a predetermined threshold, by the reading and control means 25. In the case where the quantity of light received by a pixel is not sufficient, the phase integration is resumed and extended, preferably after the photosensitive element PD has been reset. For example, the integration phase is extended by a duration corresponding to its initial duration. Because the first reading of the mem-j_ areas is not destructive, the electrons accumulated during the initial integration phase are always present in the mem-j_ areas and the electrons transferred to these mem-j_ areas during the extension of the integration phase are added to the electrons already present. Once the extended integration phase is completed, a new pixel reading phase is implemented from the
    B15739 FR - 16-GR3-0522 as described in relation to FIG. 3. Of course, as long as the quantity of light received by the pixel is not sufficient, the integration phase can be extended again as described below. above.
    Thus, in a TOF sensor comprising pixels of the type of that of FIG. 2, the duration of the integration phase can be dynamically adjusted for each pixel of the sensor as a function of the light received by this pixel. This dynamic adaptation of the duration of the integration phase for each pixel of the sensor is made possible by the fact that the reading of the memy storage areas of the pixel is not destructive.
    An embodiment of a pixel of the type of that of FIG. 2 will now be described in more detail in relation to FIGS. 4A to 4D.
    FIGS. 4A to 4D schematically represent an exemplary embodiment of the pixel TOF of FIG. 2. FIG. 4A is a top view of the pixel, FIGS. 4B and 4C are section views respectively along the planes BB and CC of the figure. 4A, and Figure 4D is a sectional view along the broken line DD of Figure 4A. In this embodiment, the pixel TOF comprises three sets Qy, with i equal to 1, 2 or 3, and a reset transistor Trespp. Each Qy set includes a Tmemy transfer transistor, a memy storage area and a Try read transistor.
    The pixel TOF comprises a photosensitive area PD, for example of square shape when viewed from above. As illustrated by FIGS. 4C and 4D, the photosensitive area PD comprises an N-type doped layer 41, of doping level Ny. The layer Ny 41 is formed at the level of the upper face of a semiconductor substrate 43 doped of type P whose doping level can decrease when one approaches the layer Ny 41.
    As illustrated by FIG. 4C, the pixel TOF also includes, in the photosensitive zone PD, an N type doped charge collection zone 45, of doping level Ny greater than Ny. The Ny 45 zone is coated with a layer 47 strongly
    B15739 FR - 16-GR3-0522 P-type doped (P + ). The zone N2 45 extends through all or part of the thickness of the layer N] _ 41. In this example, the charge collection zone N2 45 penetrates into the substrate P 43 deeper than the layer N] _ 41.
    As illustrated by FIGS. 4A, 4B and 4D, each mem-j_ storage area is delimited by an insulated conductive wall (or insulated vertical electrode) 49. More particularly, each mem-j_ storage area extends from of a portion 41A of the layer 41 entirely coated with the gate 51 of the corresponding transfer transistor Tmem-j_. The grid 51 is separated from this portion N] _ 41A by a layer of grid insulation 53. In this embodiment, as illustrated in FIG. 4A, each storage zone mem-j_ extends along d an edge of the photosensitive zone PD, and the electrode 49 delimiting the mem-j_ zone on the side of the photosensitive zone PD also delimits this edge of the photosensitive zone PD. In addition, the electrodes 49 laterally delimiting each mem-j_ storage area are connected to each other by an electrode 55 corresponding to an extension of the electrodes 49. The electrode 55 laterally delimits the mem-j_ storage area of the opposite side to the corresponding portion 41A.
    As illustrated by FIGS. 4B and 4C, the insulated walls 49, 55 extend from the upper face of the pixel, pass through the layer N] _ 41 and penetrate into the substrate P 43. These walls 49, 55 comprise a material conductor 57, for example doped polycrystalline silicon, bordered by an insulating layer 59, for example of silicon oxide.
    Each storage zone mem-j_ comprises, as illustrated by FIGS. 4B and 4D, an N-type doped well 61, of doping level N5 greater than that of the layer N] _ 41. Each well N5 61 enters the substrate 43 to a depth greater than or equal to that of the layer N] _ 41 and less than that of the isolated electrodes 49, 55. Each well N5 61 includes a portion 61A coated with the gate 63 of the corresponding reading transistor Tr-j_ , the grid 63 being separated from the box 61 by a layer of grid insulator 65. The grid 63 is a grid
    B15739 FR - 16-GR3-0522 annular surrounding a heavily doped P + type area 67 and penetrating over part of the thickness of the N5 box 61. The annular grid 63 preferably extends from one to the other walls 49 laterally delimiting the corresponding memy storage area. In this example, the portion 61A of the box N5 61 is on the side of the portion 41A of the layer Ny 41, as shown in FIG. 4D. Each memy zone is coated with the P + layer 47 with the exception of the portion 61A of the well N5 61 coated with the annular gate 63. For each Try transistor, the zone 67 constitutes the source region of the transistor, the P + layer 47 around the gate 61 of the transistor constitutes the drain region of the transistor, and the well 61 forms the body region of the transistor.
    Each memy storage area includes an insulated vertical electrode or wall 69 disposed in the corresponding N5 box 61, beyond the portion 61A. The electrode 69 is made of the same materials and penetrates into the substrate to the same depth as the electrodes 49 and 55. In this embodiment, the electrode is parallel to the electrodes 49 delimiting the memy zone and is arranged at equal distance from each of these electrodes 49. In FIG. 4D, the electrode is not visible but its contours have been shown in dotted lines. The electrode 69 is a memy zone reset electrode.
    As illustrated in FIG. 4D, each memy zone further comprises an N-type doped zone 71, of doping level Ny greater than Ny and less than N5, the zone 71 being adjacent to the corresponding portion 41A. Each zone Ny 71 penetrates into the substrate P 43, for example over a depth greater than or equal to that of the layer Ny 41 and less than or equal to that of the wells N5 61. In the example shown, zone 71 is interposed between the portion 41A and the box N5 61 with which it is in contact. As a variant, the zone 71 can be formed in the box N5 61 which then extends to the portion Ny 41A. As a further variant, the zone 71 can be omitted,
    B15739 FR - 16-GR3-0522 and, in this case, the N5 61 box comes into contact with the N portion! 41A.
    Each portion N3 41A comprises a zone 73 of doping level N3 greater than N] _ and less than N4, N5 and N2. The zone 73 is coated with the gate 51 of the corresponding transistor Tmem-j_, and is adjacent to a corresponding storage zone mem-j_. These zones N3 73 penetrate into the substrate P 43, for example over a depth substantially equal to that of the layer N] _ 41. As a variant, the portion N] _ 41A can be devoid of zone N3 73.
    As shown in FIG. 4D, from the charge collection zone N2 45 and up to an electrode 55, extend successively and in pairs, the charge collection zone N2 45, a portion N ] _ 41A, a zone N3 73, a zone N4 71, and a box N5 61.
    The reset transistor Trespp of the pixel TOF comprises, as shown in FIG. 4C, a heavily doped drain area 75 of type N (N + ) extending from an edge of the photosensitive area PD, preferably an edge from which no mem-j_ storage area extends. The drain area N + 75 extends more particularly from a portion 41B of the layer N] _ 41 entirely coated with the gate 77 of the Trespp transistor, the gate 77 being separated from this portion N] _ 41B of the photosensitive zone PD by a layer of gate insulator 79. The drain zone N + 75 is for example formed in the layer N4 41, outside the photosensitive zone PD.
    In top view illustrated by FIG. 4A, the drain area N + 75 extends in length from the area PD to an isolated vertical electrode 81 aligned with the electrode 55 of a neighboring area mem-j_, the meim area in the example shown, and in width between an electrode 49 delimiting this neighboring mem-j_ area and a portion of a vertical annular insulated electrode 83. The electrodes 81 and 83 are made of the same materials and penetrate into the substrate on the same depth than the electrodes 49, 55 and 69. The annular electrode 83 delimits a rectangular region 85 extending along the edge of the photosensitive zone PD from
    B15739 FR - 16-GR3-0522 from which the drain zone 75 extends. Transistors not shown, for example the Tselj_ transistors, can be formed in region 85. The dimensions and arrangement of the mem-j_ zones, of the drain area 75 and the region 85 are preferably chosen so that the pixel has the shape of a square in top view as illustrated by FIG. 4A. In practice, as illustrated in FIG. 4A, the walls 49, 55, 81 and 83 are portions of the same wall which entirely delimits the periphery of the pixel, portions of this wall being able to be shared by several adjacent pixels.
    As can be seen in FIG. 4A, the charge collection zone 45 has the shape of a cross comprising a central portion disposed at the center of the photosensitive zone, and arms extending from this central portion, between the grids 51, 77 resting on the photosensitive zone. The thicknesses and the materials of the gates of the transistors Tmem-j_ and Trespp can then be chosen so that these gates are transparent to the radiations of the light signal Lp received by the pixel. In addition, these thicknesses and these materials can be chosen so that these grids filter at least part of the parasitic light radiation having wavelengths distant from those of the signal Lr.
    A light opaque screen (not shown) comprising an opening facing the photosensitive zone PD is provided above the pixel. Thus, the radiation of the light signal Lp only reaches the photosensitive area PD of the pixel.
    In operation, the electrodes 49, 55, 81 and 85 are connected to a negative or zero potential, for example - 1 V, so that holes accumulate along their walls. This reduces dark currents. This also makes it possible to put the layer P + 47 and the substrate P 43 at the same low reference potential, for example the mass, applied to the substrate 43 or to the layer 47. By default, the signal Vres applied to the conductive material 57 of the electrodes 69 is in the low state corresponding to a negative or zero potential, for example the same potential as
    B15739 FR - 16-GR3-0522 the one applied to the other vertical electrodes isolated from the pixel. It results from the polarization of the isolated vertical electrodes that the photosensitive zone PD and the storage zones mem-j_ then correspond to so-called pinched diodes. The doping levels of the photosensitive zone PD and of the storage zones mem-j_ are chosen so that, in the absence of illumination, these pinched diodes are completely depleted.
    A transfer phase between the photosensitive zone PD and a mem-j_ zone will now be described in more detail in relation to FIGS. 5A to 5C.
    FIGS. 5A to 5C schematically represent the evolution of the levels of the electrostatic potentials along the broken line DD of FIG. 4A, as a function of the on or off state of the corresponding transistor Tmem-j_. These FIGS. 5A to 5C are plotted on the same horizontal scale as FIG. 4D. In these figures, the electrostatic potentials are increasing from top to bottom.
    For control signals Vmem-j_ in the low state (for example at ground), because the doping levels N] _, N3, N4, N5 are increasing, the electrostatic potentials VIA, V3, V4, V5 respectively in the portions 41A, the area N3 73, the area Ng 71, and the box N5 61 are increasing. In addition, since the doping level N2 is higher than the levels N] _ and N3, the electrostatic potential V2 in the charge collection zone is higher than the electrostatic potentials VIA and V3.
    In the housing N5 61, the further one moves away from the walls of the electrodes 49, 55 and 69 where the electrostatic potential is low and fixed by the holes accumulated along these walls, the higher the electrostatic potential. As a result, the well N5 61 has a lower potential level in the portion of the well where the reset electrode 69 is formed than in the portion 61A. Thus, the electrons which are transferred from the photosensitive zone PD first accumulate in this portion 61A. As a result, even the transfer of a small amount of electrons into the mem-j_ area results in a change in the
    B15739 FR - 16-GR3-0522 threshold voltage of the corresponding transistor Trg. The reset electrode 69 therefore advantageously makes it possible to increase the sensitivity of the pixel.
    In the step of FIG. 5A, the transistor Tmemg is in the blocked state. The potential of the signal Vmemg in the low state is chosen so that the potentials VIA and V3 remain lower than the potentials V2 and V4. Although this is not shown in these figures, the Vrespp signal is in the low state and at the same potential as the Vmemg signals, from which it follows that the electrostatic potential in the portion Ng 41B (see FIG. 4C) under the gate 77 of the transistor Trespp is the same as the potential VIA in the portions Ng 41A under the gates 51 of the transistors Tmemg. Thus, the photogenerated electrons remain confined in the Ng zone.
    In the step of FIG. 5B, the transistor Tmemg is set to the on state so that the potential VIA and the potential V3 become greater than the potentials V2 and V4. As a result, the electrons accumulated in the charge collection area Ng 45 are all transferred to the area N3 73 where they are temporarily stored, blocked between the potential barriers VIA and V4. The electrons (not shown) which have already been transferred to the memg storage area during previous transfers remain confined in the well N5 by the potential barrier V4.
    In the step of FIG. 5C, the transistor Tmemg is returned to the blocked state, which causes the potentials VIA and V3 to again become lower than the potentials V4 (and V5). The electrons which were in zone N3 73 are then all transferred to the corresponding chamber N5 61, through zone N4 71. Advantageously, the potential VIA forms a potential barrier preventing the return of electrons from zone N3 71 towards the Ng 45 charge collection zone.
    We have previously described in relation to FIG. 3 a phase of resetting to zero the memg zones consisting of several successive switches of the signal Vres between a negative potential
    B15739 FR - 16-GR3-0522 and a positive potential. In the pixel of FIGS. 4A to 4D, this signal is applied to the conductive material of the reset electrodes 69. It then results from these successive switching operations that the electrons accumulated in the memy zones recombine along the walls of the electrodes 69, and are removed from the memy zones to the P + 47 layer and / or the P 43 substrate.
    Advantageously, the provision of a reset electrode 69 in the box 61 of the memy area makes it possible to prevent the reset of the memy area from being done by applying a very high potential to the gate 51 of the try transistor, for example more than 5 V. This reset electrode 69 also makes it possible to avoid resetting the memy area to zero by applying the signal Vres to the electrodes 49 which would modify the behavior of the photosensitive area PD of the pixel and / or would influence adjacent pixels sharing portions of these electrodes 49.
    Another advantage of the embodiments described above is that, by default, each Try transistor is in the on state, resulting in an accumulation of holes under its gate 63. This accumulation of holes, between the P + 47 layer and the corresponding zone 67 is then at the same potential as the layer 47 and makes it possible to reduce the dark currents, in particular during the integration phases.
    In the embodiment described above in relation to FIGS. 4A to 4D, each memy zone comprises only a single reset electrode 69, disposed between the corresponding electrodes 49, parallel to them and equidistant from each of the electrodes 49. A person skilled in the art is able to modify the number and / or the arrangement of these reset electrodes in the storage zone as a function of the shape of the well of electrostatic potential which he wishes to obtain in this memy area. Preferably, as described above, a person skilled in the art will choose a number and / or an arrangement of reset electrodes which make it possible to obtain a deeper potential well under the gate of the corresponding Try transistor. .
    B15739 FR - 16-GR3-0522
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, the substrate 43 can be N-type doped, at a doping level lower than N] _, and it can then have an increasing doping level up to the N] _ layer 41.
    Similarly to what has been described for the N] _ 41A portions, the N] _ 41B portion of the Trespp transistor may include an N3 area 73 adjacent to the N + 75 area to improve the charge transfer controlled by the Trespp transistor .
    As indicated above, the number of sets Qj_ can be chosen to be greater than 3, possibly by providing that the photosensitive zone has the shape of a polygon, for example a regular polygon, other than a square. For example, in a pixel comprising five sets Qj_ and a reset transistor Trespp, the photosensitive area PD has for example a substantially hexagonal shape. It can also be provided that each pixel comprises only two sets Qj_ which is sufficient to calculate the phase shift φ.
    More generally, the shape, the number and the arrangement of the various constituent elements of the pixel TOF described in relation to FIGS. 4A to 4D can be modified. For example, provision could be made for each mem-j_ storage area not to extend along an edge of the photosensitive area PD but rather orthogonally to this edge.
    Although we have described here types of conductivity for the various zones, layers and wells of a pixel in the case where the photogenerated charges accumulated, collected, transferred, stored and read are electrons, these types of conductivity can all be inverted so that these charges are holes. Those skilled in the art will then be able to adapt the command potentials applied to the various transistors of the pixel.
    An operating mode has been described above in which the Trespp transistor is only used as a reset transistor for the photosensitive area. A person skilled in the art is able to modify the potential applied to the grid of the
    B15739 FR - 16-GR3-0522 Trespp transistor in the blocked state so that an excess of photogenerated electrons in the photosensitive zone PD is evacuated towards the N + 71 region rather than towards a storage zone mem-j_, the Trespp transistor then being used as anti-glare transistor in addition to serving as a reset transistor of the photosensitive area PD.
    Various embodiments with various variants have been described above. Note that those skilled in the art can combine various elements of these various embodiments and variants without showing inventive step.
    B15739 FR - 16-GR3-0522
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    1. Time-of-flight detection sensor comprising a plurality of pixels, each pixel comprising a photosensitive area (PD) and at least two sets (Q-j_) each comprising:
    a charge storage area (mem-dd;
    a transfer transistor (Tmem-j_) adapted to control charge transfers from the photosensitive area (PD) to the charge storage area; and a reading means capable of non-destructively measuring the quantity of charges stored in the storage area.
    [2" id="c-fr-0002]
    2. Sensor according to claim 1, in which the reading means comprises:
    a read transistor (Tr-j_) whose body corresponds to the charge storage area (mern-J;
    a constant current source (23) supplying the read transistor; and a means for measuring (LECT, 25) the voltage across the terminals of the transistor.
    [3" id="c-fr-0003]
    3. Sensor according to claim 1 or 2, further comprising control means (25) for repeating a transfer of charges to the storage area if the quantity of charges transferred is insufficient to be measured.
    [4" id="c-fr-0004]
    4. The sensor of claim 2, wherein each read transistor (Tr-jJ is coupled to the current source via a selection transistor (Tsel-jJ.
    [5" id="c-fr-0005]
    5. Sensor according to any one of claims 1 to 4, wherein each storage area (mem-j_) contains an insulated conductive reset wall (69).
    [6" id="c-fr-0006]
    6. Image sensor according to any one of claims 1 to 5, comprising a source for transmitting a periodic light signal (Lj ), And means (15, 25) adapted to synchronize said source and potentials of control applied to the transistor grids (Tmem-j_) of each pixel.
    B15739 FR - 16-GR3-0522
    [7" id="c-fr-0007]
    7. Time-of-flight detection pixel of a sensor according to claim 1, comprising a semiconductor substrate (43), in which:
    the photosensitive zone (PD) comprises a first layer (41) doped with a first type of conductivity;
    each charge storage zone (memg) extends from an edge of the photosensitive zone, from a first portion (41A) of the first layer coated with the gate (51) of the corresponding transfer transistor (Tmemg), the charge storage area comprising a box (61) more heavily doped of the first type than the first layer, and being delimited laterally by two vertical insulated conductive walls (49), parallel and facing each other ;
    for each box, an annular grid (63) covers a portion (61A) of said box and surrounds a heavily doped area (67) of the second type penetrating into the box and being coupled to a constant current source (23) of the sensor; and a second doped layer of the second type (47) covers the charge storage zones and the photosensitive zone with the exception of the portions (41A, 41B, 61A) coated with grids (51, 77, 63).
    [8" id="c-fr-0008]
    8. A pixel according to claim 7, in which each storage area (memg) further comprises an insulated vertical conductive wall (69) for resetting, disposed between said two insulated conductive vertical walls (49), in a portion of the box. (61) other than the portion (61A) coated with the annular grid (63).
    [9" id="c-fr-0009]
    9. A pixel according to claim 7 or 8, in which each first portion (41A) of the first layer comprises a first intermediate zone (73) adjacent to the corresponding storage zone (memg), the first intermediate zone being doped of the first type. , more strongly than the rest of the first layer and less strongly than the box (61) of the storage area.
    [10" id="c-fr-0010]
    10. Pixel according to any one of claims 7 to 9, in which each charge storage area (memg) comprises
    B15739 FR - 16-GR3-0522 a second intermediate zone (71), inserted between the box (61) of the storage zone and the photosensitive zone (PD), the second intermediate zone being doped with the first type, more strongly than the first portion (41A) and less strongly than the box.
    [11" id="c-fr-0011]
    11. Pixel according to any one of claims 7 to
    10, wherein the photosensitive area (PD) has the shape of a square in top view, and each storage area (memy) extends along an edge of the photosensitive area.
    [12" id="c-fr-0012]
    12. Pixel according to any one of claims 7 to
    11, in which the first layer (41) rests on a portion of the doped substrate (43) of the second type and the doping level of which decreases as it approaches the first layer.
    [13" id="c-fr-0013]
    13. Pixel according to any one of claims 7 to
    12, further comprising a reset zone (75) more heavily doped of the first type than the photosensitive zone (PD), extending from an edge of the photosensitive zone, from a second portion (41B) of the first layer (41) coated with a second grid (77).
    [14" id="c-fr-0014]
    14. Pixel according to any one of claims 7 to
    13, in which the photosensitive zone (PD) further comprises a charge collection zone (47) comprising a central portion disposed substantially in the center of the photosensitive zone, and arms extending from this central portion, between the grids (51, 77) coating said portions (41A, 41B) of the first layer (41).
    [15" id="c-fr-0015]
    15. Pixel according to any one of claims 7 to
    14, intended to receive a periodic light signal (Lr), in which the grids (51, 77) coating said portions (41A, 41B) of the first layer (41) are made of materials transparent to the wavelengths of the periodic signal received.
    B 15739 FR
    [16" id="c-fr-0016]
    16-GR3-0522
    1/4
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    FR3065320B1|2020-02-07|
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    引用文献:
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    法律状态:
    2018-03-22| PLFP| Fee payment|Year of fee payment: 2 |
    2018-10-19| PLSC| Search report ready|Effective date: 20181019 |
    2019-03-25| PLFP| Fee payment|Year of fee payment: 3 |
    2020-03-19| PLFP| Fee payment|Year of fee payment: 4 |
    2021-03-23| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1753344|2017-04-18|
    FR1753344A|FR3065320B1|2017-04-18|2017-04-18|FLIGHT TIME DETECTION PIXEL|FR1753344A| FR3065320B1|2017-04-18|2017-04-18|FLIGHT TIME DETECTION PIXEL|
    US15/953,925| US10951844B2|2017-04-18|2018-04-16|Time-of-flight detection pixel|
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